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    <title>CPU on Anekoique&#39;s Blog</title>
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      <title>Memory Consistency</title>
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      <description>Memory consistency models define which reorderings are legal. A walk through SC, TSO (x86), PSO, and relaxed models (ARM / POWER), plus the memory barriers used to enforce ordering when it matters.</description>
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      <title>Cache Coherence</title>
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      <description>How multi-core CPUs keep a consistent view of memory — the MESI protocol, bus snooping, cache-to-cache transfers, and the store-buffer / invalid-queue optimizations (plus the memory-ordering headaches they introduce).</description>
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